1. Field of the Invention
The present invention relates to semiconductor integrated circuits suitable for use in voltage controlled oscillators and more particularly to a semiconductor integrated circuit that can deliver stable oscillation frequencies while providing for a reduced area occupied by inductors.
2. Description of the Related Art
Conventionally, a voltage controlled oscillator (VCO) has been available that is built in high-frequency semiconductor devices or the like. FIG. 1 is a circuit diagram illustrating a prior art voltage controlled oscillator.
In the prior art voltage controlled oscillator, the drains of transistors Tr1 and Tr2 are connected to a constant current power supply S1. Inductors L1 and L2 are each connected at one end thereof to a power supply line through which a power supply voltage VDD is provided. The inductance of the inductor L1 is equal to that of the inductor L2. On the other hand, the inductor L1 is connected at the other end thereof with a varactor diode D1, the source of the transistor Tr1, and the gate of the transistor Tr2, while the inductor L2 is connected at the other end thereof with a varactor diode D2, the source of the transistor Tr2, and the gate of the transistor Tr1. An analog control voltage is applied to the varactor diodes D1 and D2.
In the prior art voltage controlled oscillator constructed as described above, it is possible to acquire an oscillation signal from the source of the transistor Tr1. However, to acquire an undistorted sinusoidal oscillation signal, the properties of the inductors L1 and L2 need to match with each other. FIG. 2 is a schematic view illustrating an exemplary structure of the inductors L1 and L2.
For example, the inductors L1 and L2 of the prior art voltage controlled oscillator comprise a circular electrically conductive layer formed on an interlayer insulating film. With this arrangement, the conductive layers need to be symmetric in a plan view with respect to a straight line passing through their midpoint position in order to allow their properties to match with each other as described above. For example, inductors configured as such are described in articles such as “A 1.8-Ghz Low-Phase-Noise CMOS VCO Using Optimized Hollow Spiral Inductors,” IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.32, NO.5, MAY 1997, or “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.36, NO.6, JUNE 2001.
On the other hand, to obtain oscillation frequencies on the order of a few hundred MHz to 10 GHz, the inductors L1 and L2 need to have an inductance on the order of 0.1 nH to a few nH. To obtain an inductance of this order, the inductors L1 and L2 need to have a diameter on the order of a few tens to a few hundreds of μm. Providing inductors of such high an inductance would cause not only their chip areas to increase but also make the inductors susceptible to disturbances such as external noise, thereby resulting in a property mismatch between both the inductors. That is, a circuit formed in the vicinity having an influence on the property of one inductor would mismatch with the other circuit formed in the vicinity having an influence on the property of the other inductor, thereby making the properties difficult to match with each other. The presence of the property mismatch makes it difficult to provide undistorted sinusoidal waves.
In this context, such an arrangement in which a double loop is formed and a half of the inner and outer loop is used to provide two inductors is disclosed in “Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.36, NO.7, JULY 2001. FIG. 3 is a layout diagram illustrating a prior art inductor pair that employs a double loop.
In the aforementioned article, as shown in FIG. 3, such an arrangement is described in which one semicircular portion acts as an outer path and the other semicircular portion acts as an inner path, thereby forming two inductors. According to such an arrangement, the area occupied by the inductors is halved, thereby making it possible to reduce chip areas and influences such as external noise.
However, concerning the arrangement shown in FIG. 3, the aforementioned article has made no mention of the three dimensional structure of the intersections of the inductors. It is possible to implement the arrangement shown in FIG. 3 by providing part of one inductor in an underlying wiring layer; however, such a structure may result in a property mismatch between the two inductors.
As shown in FIG. 4, an odd number of total windings of the two inductors may not cause a property mismatch between the two inductors; however, an even number of total windings inevitably results in a property mismatch. Although not illustrated in FIG. 4, the use of this arrangement requires a power supply line for supplying a power supply voltage to the inductors.